Aspects of the present invention relate generally to the field of integrated circuit design, and more specifically to systems and methods to optimize a design layout.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
As part of the circuit design, collections of shapes forming features or devices are inserted into the circuit design to perform a desired function. The connections between the features or devices on the circuit are defined with a netlist.
After or during the design and creation of an IC layout, validation and/or optimization operations are often performed on the IC layout using a set of testing, analysis and validation tools. These operations are conventionally performed in part to detect variations in the as-designed layout that may occur during printing due to the optical and/or chemical nature of the processing used to manufacture the IC and to otherwise ensure compliance with certain predefined design rule constraints. For example, as part of the optimization process, the proximity of two elements in a design may trigger an abutment process wherein the elements are adjusted, resized, realigned, or merged. During layout optimization, where the connected features exist in the design such that the connection between the features includes shapes that are overlapping, the shapes may be adjusted such that the overlapping shapes share an associated pin.
In advanced node technologies, the transistor size can be very small. As a result, space for external connections to the devices can be limited. In traditional vertical pin connections, the pin of a transistor is constructed parallel to its gate direction. However, with the small transistor size used in current designs, the design rule constraints limiting channel length often require an alternate configuration. In such designs, a horizontal pin connection style that constructs pins perpendicular to a transistor's gate direction is introduced to overcome the layout constraints for devices with small channel length. Traditional abutment rules and processes automatically overlap, align, and connect transistors with horizontal pins. However, such alignments and connections will often result in a connection short.
Accordingly, there is a need in the art for an improved abutment procedure for transistors having horizontal pins.